Zarrin Tasnim Sworna
(Lecturer)Department of Computer Science and Engineering
| Degree Name | Group/Major Subject | Board/Institute | Country | Passing Year |
|---|---|---|---|---|
| Masters | University of Dhaka | Bangladesh | 2016 | |
| Bachelor | University of Dhaka | Bangladesh | 2014 |
| Title | Organization | Location | From Date | To Date |
|---|---|---|---|---|
| Lecturer | University of Dhaka | 01, Mar 2018 | Currently Working |
Research Interest
| Subject | Description | Research Interest (Goal, Target Indicator) |
|---|---|---|
| Cyber Security | ||
| VLSI | ||
| HCI |
Project/Research Supervision
| Level of Study | Title | Supervisor | Co-Supervisor(s) | Name of Student(s) | Area of Research | Current Completion |
|---|---|---|---|---|---|---|
| No project/research supervision is found | ||||||
Project/Research Work
| Subject | Project Name | Source of Fund | From Date | To Date | Collaboration |
|---|---|---|---|---|---|
| No project/research work is found | |||||
Invited Talk
| SL | Invited Talk |
|---|---|
| No invited talk is found | |
| SL | Collaboration & Membership Name | Type | Membership Year | Expire Year |
|---|---|---|---|---|
| No Collaboration & Membership is found | ||||
| Journal Article | |
|---|---|
| 1 |
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md Hasan Babu, and Ashis Kumar Biswas. : A Fast FPGA-Based BCD Adder,
Circuits, Systems, and Signal Processing, Springer, New York, United States , vol.37 , no.10 , pp.4384-4408 , 2018
.
|
| 2 |
Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md Hasan Babu and Ashis Kumar Biswas : Low-power and area effcient binary coded decimal adder design using a look up table-based eld programmable gate array,
IET Circuits,Devices & Systems (United Kingdom) , vol.10 , no.3 , pp.163-172 , 2016
.
|
| Conference Proceedings | |
| 1 |
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu, and Lafa Jamal "A Cost-Efficient LUT-Based BCD Adder Design."
IEEE Future Technologies Conference (FTC)
, pp. 874-882. Vancuover, Canada: IEEE, 2017
.
|
| 2 |
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu, Lafa Jamal, and Ashis Kumer Biswas "An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem."
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
, pp. 116-121. Bochum, Germany: IEEE, 2017
.
|
| 3 |
Zarrin Tasnim Sworna, Mubin Ul Haque and Hafiz Md Hasan Babu "A LUT-based matrix multiplication using neural networks."
IEEE International Symposium on Circuits and Systems (ISCAS)
, pp. 1982-1985. Montreal, Canada: IEEE, 2016
.
|
| Award Type | Title | Year | Country | Description |
|---|---|---|---|---|
| No award information is found | ||||
Zarrin Tasnim Sworna
Lecturer
Department of Computer Science and Engineering
Faculty of Engineering and Technology
Email: zarrinsworna@gmail.com